Nicolas Rault-Wang

Nicolas Rault-Wang

UC Berkeley Applied Math & CS undergraduate researching computational imaging, machine learning for scientific instrumentation, and large-scale data systems at the Space Sciences Laboratory.

Research Focus

I develop machine learning systems and computational methods for scientific instrumentation, with expertise spanning computer vision, distributed systems, and hardware-software co-design. My research bridges theoretical mathematics with practical implementation to solve challenging problems in astronomical data analysis and real-time transient detection.

Computational Imaging Machine Learning Systems Scientific Instrumentation Large-Scale Data Systems

Publications & Presentations

Nanosecond differential timing using inexpensive differential GNSS receivers (DRAFT)

B. Godfrey, W. Liu, N. Rault-Wang, J. Kocz, D. Werthimer

2025 United States National Committee of URSI National Radio Science Meeting (USNC-URSI NRSM), Jan. 2025, 431–431.

DOI: 10.23919/USNC-URSINRSM66067.2025.10906985

Machine learning applications for anomaly and interference detection on PANOSETI data

N. Rault-Wang, Y. Dong, W. Liu, D. Werthimer, J. Maire, and S. Wright

PANOSETI Collaboration Meeting (Plenary Talk), San Diego, CA, United States, Jan. 2025.

DOI: 10.5281/zenodo.17388495

Identifying clouds in panoramic SETI data with machine learning

N. Rault-Wang, et al.

2024 Assembly of the Order of the Octopus (Poster Presentation), Green Bank, WV, United States, Aug. 2024.

DOI 10.5281/zenodo.14590904

Research Projects

Deep Learning for PANOSETI

Computer Vision

Designed and implemented the first deep learning pipeline for the PANOSETI collaboration, achieving 95% classification accuracy and 0.97 average precision in automated interference detection for the project’s daily terabyte-scale datasets of wide-field, 20μs-integration optical/near-IR images.

PyTorch Computer Vision Real-time Systems
View → Conference Poster or Technical Summary

High-speed Data Acquisition System

Systems

Developed and maintained an ultra-high data rate (100k frames/sec) C++ acquisition pipeline, integrating an asynchronous gRPC API, leading several extensibility-focused refactors, and establishing a full GitHub Actions CI pipeline to validate fault-tolerance and >99.99% data integrity.

C++ HASHPIPE High-performance gRPC CI Testing
View System Overview, gRPC API, or HASHPIPE

Terabyte-scale Data Pipeline

Distributed Systems

Co-designed and implemented a scalable data reduction pipeline (TensorStore, Zarr, Dask) for terabyte-scale datasets, leading technical prototyping from a self-administered 12TiB BeeGFS cluster to San Diego Supercomputer Center HPC facilities.

BeeGFS Dask HPC
View Cluster Setup →

Unsupervised Anomaly Detection

Computer Vision

Proposed and prototyped an unsupervised anomaly detector using a β-Variational Autoencoder, capable of clustering Cherenkov events, noise, and stellar signals based on low-dimensional latent embeddings.

PyTorch VAE Anomaly Detection Clustering
View Write-up →

Education

University of California, Berkeley

Aug 2021 – Dec 2025

Bachelor of Arts, double major in Applied Mathematics and Computer Science

GPA: 3.88

Relevant Coursework:

Deep Neural Networks (CS 182) Machine Learning (CS 189) Computer Vision (CS 180) Optimization Models (EECS 127) Probability Theory (DATA 140) Real Analysis (MATH 104) Complex Analysis (MATH H185) Digital Signal Processing (EE 123) Operating Systems (CS 162) Computer Architecture (CS 152) Digital Design and Integrated Circuits (EECS 151) Quantum Mechanics (PHYSICS 137A)

Advanced Coursework and Projects

CS 180: Computer Vision & Computational Photography

The following are write-ups from my CS 180 projects, each of which reproduces results from key papers in computer vision.

EECS 151: Introduction to Digital Design and Integrated Circuits

Awarded 1st Place in a Spring 2025 Apple-sponsored RISC-V CPU design contest in a team with Neel Gajare, out of 18 two-person teams. We achieved the highest figure-of-merit in the FPGA category over the past 2 years with a compact design featuring a 1.06 CPI and 125 MHz clock frequency on a Xilinx 7 Series FPGA.
I led the design of advanced optimizations and Verilog implementation, resulting in a fully bypassed, 5-stage RISC-V pipeline with speculative execution provided by a branch target buffer. See our write-up at the link below!

Get In Touch

I'm currently exploring PhD opportunities in computational imaging and machine learning systems. Feel free to reach out if you're interested in collaboration or discussion.