Nicolas Rault-Wang
Ph.D. Student, MIT EECS (starting Fall 2026) • B.A.s in Applied Math and Computer Science, UC Berkeley ('25)
I build distributed, high-speed data acquisition systems and machine learning pipelines for scientific instruments.
With Prof. Dan Werthimer at Berkeley's Space Sciences Laboratory, I built PANOSETI's distributed control and terabyte-scale acquisition systems and its ML pipelines for interference and anomaly detection — work that carried the project from a 3-telescope prototype at Lick Observatory to a 4+ telescope production deployment at Palomar.
With Prof. Andrew Howard at Caltech, I architected the California Planet Search's next-generation data platform, Jump 2.0, to accelerate precision radial-velocity analysis of Keck Planet Finder datasets.
This fall I join MIT EECS's Signal Kinetics group, where I intend to pursue research with Prof. Fadel Adib on new wireless sensing and communication technologies.
Selected Work
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Deep Learning for PANOSETIDesigned and implemented the first deep-learning pipeline for the PANOSETI collaboration, achieving 95% classification accuracy and 0.97 average precision in automated interference detection for daily terabyte-scale datasets of wide-field, 20 μs-integration optical/near-IR images.
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High-speed Data Acquisition SystemDeveloped and maintained an ultra-high data-rate (100k frames/sec) C++ acquisition pipeline, integrating an asynchronous gRPC API, leading several extensibility-focused refactors, and establishing a self-hosted hardware-software GitHub Actions CI pipeline to validate fault-tolerance and >99.99% data integrity.
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Terabyte-scale Data PipelineCo-designed and implemented a scalable data-reduction pipeline (Zarr, Ray, Nextflow) for terabyte-scale datasets and real-time classification, leading technical prototyping from a self-administered 4-GPU cluster to San Diego Supercomputer Center facilities.
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Apple-Sponsored RISC-V CPU Design Contest (1st Place)Awarded 1st place (of 18 teams) in a Spring 2025 Apple-sponsored contest with the best PPA metrics over two years: lowest resource utilization, 1.06 CPI, 125 MHz clock. I led the microarchitecture design, implementation, and validation of a fully bypassed, 5-stage RISC-V pipeline with speculative execution (BTB+gShare).