Nicolas Rault-Wang

Nicolas Rault-Wang

BA double major in Applied Math & CS, UC Berkeley ('25) • Post-Bac Researcher, Caltech (Jan 2026 - present) • Incoming PhD Student, MIT EECS (Fall 2026)

I build distributed, high-speed data acquisition systems and machine learning pipelines for scientific instruments.
With Prof. Dan Werthimer at Berkeley's Space Sciences Lab, I led development of PANOSETI's production distributed control and terabyte-scale acquisition systems, its real-time and HPC analysis pipelines, and custom and linear-probed ML models for interference and anomaly detection, supporting its gamma-ray astronomy and optical SETI science cases. With Prof. Andrew Howard at Caltech, I led development of the Keck Planet Finder's next-generation data analysis portal, Jump 2.0, for precision radial-velocity exoplanet science.
This fall, I bring my cross-domain astronomy sensing background to MIT EECS's Signal Kinetics group, where I intend to pursue research with Prof. Fadel Adib at the intersection of wireless sensing and computational imaging.

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Selected Work

  • Deep Learning for PANOSETI
    Computer Vision · PyTorch · Real-time Systems · UC Berkeley SSL
    Designed and implemented the first deep-learning pipeline for the PANOSETI collaboration, achieving 95% classification accuracy and 0.97 average precision in automated interference detection for daily terabyte-scale datasets of wide-field, 20 μs-integration optical/near-IR images.
    [Conference Poster] [Technical Summary]
  • High-speed Data Acquisition System
    Systems · C++ · HASHPIPE · gRPC · UC Berkeley SSL
    Developed and maintained an ultra-high data-rate (100k frames/sec) C++ acquisition pipeline, integrating an asynchronous gRPC API, leading several extensibility-focused refactors, and establishing a self-hosted hardware-software GitHub Actions CI pipeline to validate fault-tolerance and >99.99% data integrity.
    [System Overview] [gRPC Repo]
  • Terabyte-scale Data Pipeline
    Distributed Systems · BeeGFS · Dask · HPC · UC Berkeley SSL
    Co-designed and implemented a scalable data-reduction pipeline (Zarr, Ray, Nextflow) for terabyte-scale datasets and real-time classification, leading technical prototyping from a self-administered 4-GPU cluster to San Diego Supercomputer Center facilities.
    [Pipeline Repo] [Cluster Setup]
  • Apple-Sponsored RISC-V CPU Design Contest (1st Place)
    Computer Architecture · Verilog RTL · Xilinx Zynq-7000 · UC Berkeley
    Awarded 1st place (of 18 teams) in a Spring 2025 Apple-sponsored contest with the best PPA metrics over two years: lowest resource utilization, 1.06 CPI, 125 MHz clock. I led the microarchitecture design, implementation, and validation of a fully bypassed, 5-stage RISC-V pipeline with speculative execution (BTB+gShare).
    [Optimization Write-Up]

Full research record →