Projects
Class projects and independent work outside my main research agenda: build-to-learn explorations, course projects, and things I’m proud of that don’t fit neatly into a lab context. Research details some of my past research.
Computer Vision & Computational Photography
Six projects from CS 180 (UC Berkeley, Fall 2024), each reproducing results from a key paper or method.
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Neural Radiance Fields & Facial Keypoint DetectionImplemented NeRF from scratch (positional encoding, volume rendering, coarse-to-fine sampling) and a convolutional facial keypoint detector trained on the IMM Face Database. -
The Power of Diffusion ModelsExplored denoising diffusion probabilistic models: sampling, DDIM, classifier-free guidance, inpainting, and training a small UNet on MNIST. -
Image Warping, Mosaicing & Auto-StitchingHomography estimation, image rectification, and panorama stitching via manual and automatic feature-point correspondence. Implemented Harris corner detection, ANMS, feature descriptor extraction, RANSAC, and the full auto-stitching pipeline. -
Face Morphing & Population StatisticsTriangulation-based face morphing, computation of mean faces from the Danes dataset, and caricature generation via extrapolation. -
Fun with Filters & FrequenciesGaussian and Laplacian stacks, hybrid images, and multiresolution blending. -
Colorizing the Prokudin-Gorskii Photo CollectionAutomatic alignment of three-channel glass-plate negatives using NCC/SSD image metrics and image pyramid search.
Hardware & Architecture
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Apple-Sponsored RISC-V CPU Design Contest (1st Place)Awarded 1st place in a Spring 2025 Apple-sponsored CPU design contest with teammate Neel Gajare. Achieved the contest’s best PPA metrics over two years: lowest resource utilization, 1.06 CPI, and 125 MHz clock frequency. Led microarchitecture and engineering workflow (Git feature-branching, regression testing) to design a fully bypassed, 5-stage RISC-V pipeline in Verilog RTL, including speculative execution via a branch target buffer. Synthesized on the PL fabric of a Xilinx Zynq-7000 (XC7Z020) and validated with a custom SystemVerilog verification suite.